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specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 TISP5XXXH3BJ overvoltage protector series tisp5070h3bj thru tisp5190h3bj forward-conducting unidirectional thyristor overvoltage protectors smb package (top view) description analogue line card and isdn protection - analogue slic - isdn u interface - isdn power supply 8 kv 10/700, 200 a 5/310 itu-t k.20/21/45 rating ion-implanted breakdown region - precise and stable voltage low voltage overshoot under surge rated for international surge wave shapes device symbol these devices are designed to limit overvoltages on the telephone and data lines. overvoltages are normally caused by a.c. powe r system or lightning flash disturbances which are induced or conducted on to the telephone line. a single device provides 2-point protecti on and is typically used for the protection of isdn power supply feeds. two devices, one for the ring output and the other for the tip ou tput, will provide protection for single supply analogue slics. a combination of three devices will give a low capacitance protector network for t he 3-point protection of isdn lines. the protector consists of a voltage-triggered unidirectional thyristor with an anti-parallel diode. negative overvoltages are i nitially clipped by breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on sta te. this low- voltage on state causes the current resulting from the overvoltage to be safely diverted through the device. the high crowbar h olding current prevents d.c. latchup as the diverted current subsides. positive overvoltages are limited by the conduction of the anti-paralle l diode. .............................................. ul recognized component device name v drm v v (bo) v tisp5070h3bj -58 -70 tisp5080h3bj -65 -80 tisp5095h3bj -75 -95 tisp5110h3bj -80 -110 tisp5115h3bj -90 -115 tisp5150h3bj -120 -150 tisp5190h3bj -160 -190 wave shape standard i ppsm a 2/10 gr-1089-core 500 8/20 ansi c62.41 300 10/160 tia-968-a 250 10/700 itu-t k.20/21/45 200 10/560 tia-968-a 160 10/1000 gr-1089-core 100 md5ufcab 12 k a sd5xad k a how to order *rohs directive 2002/95/ec jan 27 2003 including annex device package carrier TISP5XXXH3BJ bj (j-bend do-214aa/smb) embossed tape reeled TISP5XXXH3BJr TISP5XXXH3BJ 5xxxh3 3000 r-s insert xxx value corresponding to protection voltages of 070, 080, 110, 115 and 150. for standard termination finish order as for lead free termination finish order as marking code std. quantity *r o h s c o m p l i a n t v e r s i o n s a v a i l a b l e
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 absolute maximum ratings, t a = 25 c (unless otherwise noted) electrical characteristics, t a = 25 c (unless otherwise noted) TISP5XXXH3BJ overvoltage protection series rating symbol value unit repetitive peak off-state voltage (see note 1) '5070h3bj '5080h3bj '5095h3bj '5110h3bj '5115h3bj '5150h3bj '5190h3bj v drm -58 -65 -75 -80 -90 -120 -160 v non-repetitive peak impulse current (see notes 2, 3 and 4) i ppsm 500 300 250 220 200 200 200 160 100 a 2/10 s (gr-1089-core, 2/10 s voltage wave shape) 8/20 s (iec 61000-4-5, 1.2/50 s voltage, 8/20 s current combination wave generator) 10/160 s (tia-968-a, 10/160 s voltage wave shape) 5/200 s (vde 0433, 10/700 s voltage waveshape) 0.2/310 s (i3124, 0.5/700 s waveshape) 5/310 s (itu-t k.44, 10/700 s voltage waveshape used in k.20/21/45) 5/310 s (ftz r12, 10/700 s voltage waveshape) 10/560 s (tia-968-a, 10/560 s voltage wave shape) 10/1000 s (gr-1089-core, 10/1000 s voltage wave shape) non-repetitive peak on-state current (see notes 2, 3 and 5) i tsm 55 60 2.1 a 20 ms, 50 hz (full sine wave) 16.7 ms, 60 hz (full sine wave) 1000 s 50 hz/60 hz a.c. initial rate of rise of on-state current, gr-1089-core 2/10 s wave shape di t /dt 400 a/ s junction temperature t j -40 to +150 c storage temperature range t stg -65 to +150 c notes: 1. see figure 9 for voltage values at lower temperatures. 2. initially the device must be in thermal equilibrium with t j = 25 c. 3. the surge may be repeated after the device returns to its initial conditions. 4. see figure 10 for current ratings at other temperatures. 5. eia/jesd51-2 environment and eia/jesd51-3 pcb with standard footprint dimensions connected with 5 a rated printed wiring track widths. derate current values at -0.61 %/ c fo r ambient temperatures above 25 c. see figure 8 for current ratings at other durations. parameter test conditions min typ max unit i drm repetitive peak off-state current v d = v drm t a = 25 c t a = 85 c -5 -10 a v (bo) breakover voltage dv/dt = -250 v/ms, r source = 300 ? '5070h3bj '5080h3bj '5095h3bj '5110h3bj '5115h3bj '5150h3bj '5190h3bj -70 -80 -95 -110 -115 -150 -190 v v (bo) impulse breakover voltage dv/dt -1000 v/ s, linear voltage ramp, maximum ramp value = -500 v di/dt = -20 a/ s, linear current ramp, maximum ramp value = -10 a '5070h3bj '5080h3bj '5095h3bj '5110h3bj '5115h3bj '5150h3bj '5190h3bj -80 -90 -105 -120 -125 -160 -200 v
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 thermal characteristics, t a = 25 c (unless otherwise noted) electrical characteristics, t a = 25 c (unless otherwise noted) (continued) TISP5XXXH3BJ overvoltage protection series i (bo) brea kover current dv/dt = -250 v/ms, r source = 300 ? -150 -600 ma v f forwar d voltage i f =5a, t w = 500 s3v v frm peak forward recovery voltage dv/dt +1000 v/ s, linear voltage ramp, maximum ramp value = +500 v di/dt = +20 a/ s, linear current ramp, maximum ramp value = +10 a 5v v t on-state voltage i t =-5a, t w = 500 s-3v i h holding current i t =- 5a , di/dt = +30 ma/ms -150 -600 ma dv/dt critical rate of rise of off-state volt age linear voltage ramp, maximum ramp value < 0.85v drm -5 kv/ s i d off-state current v d = -50 v t a = 85 c -10 a c o off-state capacitance (see note 6) f = 1 mhz, v d = 1 v rms, v d = -1 v '5070h3bj '5080h3bj '5095h3bj '5110h3bj '5115h3bj '5150h3bj '5190h3bj 300 280 260 240 214 140 140 420 390 365 335 300 195 195 pf f = 1 mhz, v d = 1 v rms, v d = -2 v '5070h3bj '5080h3bj '5095h3bj '5110h3bj '5115h3bj '5150h3bj '5190h3bj 260 245 225 205 180 120 120 365 345 315 285 250 170 170 f = 1 mhz, v d = 1 v rms, v d = -50 v '5070h3bj '5080h3bj '5095h3bj '5110h3bj '5115h3bj '5150h3bj '5190h3bj 90 80 73 65 56 35 35 125 110 100 90 80 50 50 f = 1 mhz, v d = 1 v rms, v d = -100 v '5150h3bj '5190h3bj 30 30 40 30 note: 6. up to 10 mhz the capacitance is essentially independent of frequency. above 10 mhz the effective capacitance is strong ly dependent on connection inductance. parameter test conditions min typ max unit r ja junction to ambient thermal resistance ei a/ jesd51-3 pcb, i t = i tsm(1000) (see note 7) 113 c/w 265 mm x 210 mm populated line card, 4-layer pcb, i t = i tsm( 1000) 50 note: 7. eia/jesd51-2 environment and pcb has standard footprint dimensions connected with 5 a rated printed wiring track widths. parameter test conditions min typ max unit
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 parameter measurement information TISP5XXXH3BJ overvoltage protection series figure 1. voltage-current characteristic for terminal pair all measurements are referenced to the thyristor anode, a (pin 1) -v i (br) v (br) v (br)m v drm i drm v d i h i t v t i trm i ppsm v (bo) i (bo) i d quadrant i forward c onduction characteristic +v +i i f v f i frm i ppsm -i quadra nt iii switc hing characteristic pm-tisp5 x xx-001-a i fsm i tsm
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 t ypical characteristics TISP5XXXH3BJ overvoltage protection series figure 2. figure 3. figure 4. figure 5. t - junction temperature - c -25 0 25 50 75 100 125 150 i d - off-state current - a 0001 001 01 1 10 100 tc5xafa v d = -50 v t j j - junction temperature - c -25 0 25 50 75 100 125 150 no rm alized breakover voltage 0.95 1.00 1.05 1.10 tc5 xaia v t , v f - on -s ta te vo lt age, forward voltage - v 0.7 1.5 2 3 4 5 7 110 i t , i f - on-state current, forward current - a 1.5 2 3 4 5 7 15 20 30 40 50 70 150 200 1 10 100 t a = 25 c t w = 100 s tc5lac v t v f t j - junction temperature - c -25 0 25 50 75 100 125 150 normalized holding current 0.4 0.5 0.6 0.7 0.8 0.9 1.5 2.0 1.0 tc5xad off-state current vs junction temperature normalized breakover voltage vs junction temperature normalized holding current vs junction temperature on-state and forward currents vs on-state and forward voltages
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 t ypical characteristics TISP5XXXH3BJ overvoltage protection series figure 6. figure 7. off-state capacitance vs off-state voltage v d - negative off-state voltage - v 123510 20 30 50 100 c off - capacitance - pf 20 30 40 50 60 70 80 90 150 200 300 100 t j = 25 c v d = 1 vrms tc 5xabba '5110 '5080 '5070 '5095 '5115 '5150 & '5190 differential off-state capacitance vs ra ted repetitive pea k off-state voltage v drm - negative repetitive peak off-state voltage - v 58 65 75 80 90 120 c - differential off-state capacitance - pf 80 90 100 110 120 130 140 150 160 170 180 190 c = c of f(-2 v) - c o ff(-50 v) tc5xaeb ' 5150 ' 5110 ' 5070 ' 5080 '5115 ' 5095
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 rating and thermal information TISP5XXXH3BJ overvoltage protection series figure 8. figure 9. figure 10. t - current duration - s 01 1 10 100 1000 i tsm (t) - n on-repetitive peak on-state current - a 1.5 2 3 4 5 6 7 8 9 15 20 30 10 ti5hac v gen = 600 vrms, 50/60 hz r gen = 1.4*v gen /i tsm(t) eia/jesd 51-2 environment eia/jesd 51-3 pcb t a = 25 c ti5xad t amin - minimu m ambient temperature - c -35 -25 -1 5-5 5 15 25 -40 -30 -20 -10 0 10 20 de ra ti ng factor 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 t a - ambi ent temperature - c -40 -30 -20 -10 0 10 2 0304050607080 impulse current - a 80 90 100 120 150 200 250 300 400 500 600 700 iec 1. 2/50, 8/20 itu-t 10/700 fcc 10/560 be llcore 2/10 be llcore 10/1000 fcc 10/160 tc5xaa non-repetitive peak on-state current vs current duration impulse rating vs ambient temperature v derating factor vs minimum ambient temperature drm
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 deployment a pplications information these devices are two terminal overvoltage protectors. they may be used either singly to limit the voltage between two points ( figure 11) or in multiples to limit the voltage at several points in a circuit (figure 12). in figure 11, the TISP5XXXH3BJ limits the maximum voltage of the negative supply to -v (bo) and +v f . this configuration can be used for protecting circuits where the voltage polarity does not reverse in normal operation. in figure 12, the two TISP5XXXH3BJ protect ors, th4 and th5, limit the maximum voltage of the slic (subscriber line interface circuit) outputs to -v (bo) and +v f . ring and test protection is given by protectors th1, th2 and th3. protectors th1 and th2 limit the maximum tip and ring wire voltages to the v (bo) of the individual protector. protector th3 limits the maximum voltage between the two conductors to its v (bo) value. if the equipment being protected has all its vulnerable components connected between the conductors and ground, then protector th3 is not required. TISP5XXXH3BJ overvoltage protection series figure 12. line card slic protection test relay ring relay slic relay test equip- ment ring generator s1a s1b r1a r1b ring wire tip wire th1 th2 th3 slic slic protection tisp5x xxh3 bj ring/test protection o ver- current protection s2a s2b s3a s3b v bat ai4xaa th4 th5 ai4xac si gnal d.c. - r1a r1b tisp5x xxh3bj figure 11. power supply protection
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 the star-connection of three TISP5XXXH3BJ protectors gives a protection circuit which has a low differential capacitance to gro und (figure 13). this example, a -100 v isdn line is protected. in figure 13, the circuit illustration a shows that protector th1 will be forwar d biased as it is connected to the most negative potential. the other two protectors, th2 and th3 will be reverse biased as protector th1 will pu ll their common connection to within 0.5 v of the negative voltage supply. illustration b shows the equivalent capacitances of the two reverse biased protectors (th2 and th3) as 29 pf each and the capac itance of the forward biased protector (th1) as 600 pf. illustration c shows the delta equivalent of the star capacitances of illustration b. the protector circuit differential capacitance will be 26 - 1 = 25 pf. in this circuit, the differential capacitance value cannot exceed the capacitance value of the ground protector (th3). a bridge circuit can be used for low capacitance differential. whatever the potential of the ring and tip conductors are in fig ure 14, the array of steering diodes, d1 through to d6, ensure that terminal 1 of protector th1 is always positive with respect to terminal 2. the p rotec tion voltage will be the sum of the protector th1, v (bo) , and the forward voltage of the appropriate series diodes. it is important to select the correct diodes. diodes d3 through to d6 divert the currents from the ring and tip lines. diodes d1 and d2 will carry the sum of the rin g and tip currents and so conduct twice the current of the other four diodes. the diodes need to be specified for forward recovery voltage, v frm , under the expected impulse conditions. (some conventional a.c. rectifiers can produce as much as 70 v of forward recovery voltage, which would be an extra 140 v added to the v (bo) of th1). in principle the bridge circuit can be extended to protect more than two conductors by adding extra legs to the bridge. TISP5XXXH3BJ overvoltage protection series a pplications information (continued) ai4xab c - 99.5 v th1 th2 th3 si gnal c - 99.5 v c 0.5 v 600 pf 29 pf 29 pf 26 pf 1 pf 26 pf a) star-connected u-interface protector b) equivalent tisp5150h3bj capacitances c) delta equivalent shows 25 pf li ne unbalance - 10 0 v - 10 0 v - 10 0 v figure 13. isdn low capacitance u-interface protection th1 ring ai5xac d1 d2 d3 d4 d5 d6 tip 1 2 figure 14. low capacitance bridge protection circuit
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 isdn device selection the etsi technical report etr 080:1993 defines several range values in terms of maximum and minimum isdn feeding voltages. the following table shows that ranges 1 and 2 can use a tisp5110h3bj protector and ranges 3 to 5 can use a tisp5150h3bj protector. impulse testing to verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various imp ulse wave forms. the table below shows some common values. if the impulse generator current exceeds the protectors current rating then a series resistance can be used to reduce the curr ent to the protectors rated value and so prevent possible failure. the required value of series resistance for a given waveform is given by the following calculations. first, the minimum total circuit impedance is found by dividing the impulse generators peak voltage by the prote ctors rated current. the impulse generators fictive impedance (generators peak voltage divided by peak short circuit current) is then sub tracted from the minimum total circuit impedance to give the required value of series resistance. in some cases the equipment will require verif ication over a temperature range. by using the rated waveform values from figure 10, the appropriate series resistor value can be calculated f or ambient temperatures in the range of -40 c to 85 c. if the devices are used in a star-connection, then the ground return protector, th3 in figure 13, will conduct the combined cur r ent of protectors th1 and th2. similarly in the bridge connection (figure 14), the protector th1 must be rated for the sum of the conductor curre nts. in these cases, it may be necessary to include some series resistance in the conductor feed to reduce the impulse current to within the protectors ratings. TISP5XXXH3BJ overvoltage protection series a pplications information range feeding voltage standoff voltage v drm v device name minimum v maximum v 15 16 9- 75 tisp5095h3bj 26 67 0 -80 tisp5110h3bj 391 99 -120 tisp5150h3bj 490 110 5 105 115 standard peak voltage setting v volt age waveshape s peak current value a current waveshape s TISP5XXXH3BJ 25 c rating a series resistance ? gr-1089-core 2500 2/10 500 2/10 500 0 1000 10/1000 100 10/1000 100 tia-968-a 1500 10/160 200 10/160 250 0 80 0 10/560 100 10/560 160 0 1500 9/720 ? 37.5 5/320 ? 200 0 1000 9/720 ? 25 5/320 ? 200 0 i3124 1500 0.5/700 37.5 0.2/310 200 0 itu-t k.20/21/45 1500 4000 6000 10/700 37.5 100 150 5/310 200 0 ? tia-968-a terminology for the waveforms produced by the itu-t recommendation k.21 10/700 impulse generator.
specifications are subject to change without notice. customers should verify actual device performance in their specific applications. january 1998 - revised february 2005 the protector characteristic off-state capacitance values are given for d.c. bias voltage, v d , values of -1 v, -2 v and -50 v. the tisp5150h3bj and tisp5190h3bj are also given for a bias of -100 v. values for other voltages may be determined from figure 6. up to 10 mhz, the capacitance is essentially independent of frequency. above 10 mhz, the effective capacitance is strongly dependent on connectio n inductance. in figure 12, the typical conductor bias voltages will be about -2 v and -50 v. figure 7 shows the differential (line unbalance ) capacitance caused by biasing one protector at -2 v and the other at -50 v. for example, the tisp5070h3bj has a differential capacitance va lue of 166 pf under these conditions. the protector should not clip or limit the voltages that occur in normal system operation. figure 9 allows the calculation of t he protector v drm value at temperatures below 25 c. the calculated value should not be less than the maximum normal system voltages. the tisp5150h3bj, with a v drm of -120 v, can be used to protect isdn feed voltages having maximum values of -99 v, -110 v and -115 v (range 3 through to range 5). these three range voltages represent 0.83 (99/120), 0.92 (110/120) and 0.96 (115/120) of the -120 v tisp5150h3bj v drm . figure 9 shows that the v drm will have decreased to 0.944 of its 25 c value at -40 c. thus, the supply feed voltages of -99 v (0.83) and -110 v (0.92) will not be clipped at temperatures down to -40 c. the -115 v (0.96) feed supply may be clipped if the ambient temperature falls below -21 c. capacitance normal system voltage levels jesd51 thermal measurement method to standardize thermal measurements, the eia (electronic industries alliance) has created the jesd51 standard. part 2 of the st andard (jesd51-2, 1995) describes the test environment. this is a 0.0283 m 3 (1 ft 3 ) cube which contains the test pcb (printed circuit board) horizontally mounted at the center. part 3 of the standard (jesd51-3, 1996) defines two test pcbs for surface mount components; one for packages smaller than 27 mm on a side and the other for packages up to 48 mm. the smb (do-214aa) measurements used the smaller 76.2 mm x 114.3 mm (3.0 ?x 4.5 ? pcb. the jesd51-3 pcbs are designed to have low effective thermal conductivity (high thermal resi stance) and r epresent a worse case condition. the pcbs used in the majority of applications will achieve lower values of thermal resistance and so can dissipate higher power levels than indicated by the jesd51 values. TISP5XXXH3BJ overvoltage protection series a pplications information the protector can withstand currents applied for times not exceeding those shown in figure 8. currents that exceed these times must be terminated or reduced to avoid protector failure. fuses, ptc (positive temperature coefficient) resistors and fusible resistors are overcurrent protection devices which can be used to reduce the current flow. protective fuses may range from a few hundred milliamperes to one ampere. in some cases it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. the c urrent versus time characteristic of the overcurrent protector must be below the line shown in figure 8. in some cases there may be a further time limit imposed by the test standard (e.g. ul 1459 wiring simulator failure). ac power testing ?isp?is a trademark of bourns, ltd., a bourns company, and is registered in u.s. patent and trademark office. ?ourns?is a registered trademark of bourns, inc. in the u.s. and other countries.

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